COJ Electronics & Communications

Performance Analysis of CNFET Based 6T SRAM

Submission: July 26, 2018; Published: September 24, 2018

DOI: 10.31031/COJEC.2018.01.000508

ISSN 2640-9739
Volume1 Issue2


CNFET is an emerging device which facilitates continuing feature size scaling trend. This novel device is predicted to outperform existing planer devices in near future owing to its unique features like ballistic transport operation, excellent carrier mobility, high current carrying capability, high stability, one dimensional band structure. In this paper, the performance of CNFET based six transistor (6T) SRAM cell has been analyzed. The effects of variations in dielectric material, oxide thickness, metal gate and CNT work function, Fermi level and chiral vector on power delay product (PDP) and static noise margin (SNM) are comprehensively analyzed. It is observed that Hafnium Silicate (HfSiO4) as dielectric material at 1nm oxide thickness yields best results in terms of stability and energy efficiency. CNT work function of 4.65eV yields most optimum PDP value of 63.59 zepto Joule. The optimum SNM value of 358mV has been obtained at a CNT work function of 4.28eV along with best PDP/SNM ratio of 5.6mV/zJ. It is also observed that Fermi level at 0.6eV gives the most promising results. The computed results indicate that (22, 0) chirality based 6T SRAM cell yield the best performance from energy efficiency point (PDP) of view along with highest SNM/PDP ratio of 6.30mV/zJ. To get more stable SRAM cell, (13, 0) chirality gives the best SNM result of 381mV.


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