Piezoelectric,Optical and Electrical Characterization of Vertical ZnO Nanowires

Oxide nanowire arrays were studied for piezoelectric applications.Such as ZnO nanowire arrays growth on silicon substrate. The effects of thermal annealing on the optical properties of ZnO nanowires were prepared on sol-gel ZnO-seed-coated substrates. AFM images were found at 130°C well aligned vertically, and the well defined crystallographic planes, providing strong evidence that the nanowire arrays orientate along the c-axis. The annealing temperature of the ZnO thin film plays an important role on the microstructure of the ZnO grains and then the growth of the ZnO nanowire arrays. From PL spectra, an evident ultraviolet near-band edge emission peak at 382nm is observed.From (I-V) characteristic that the material behaves p-n junction diode, ideality factors >>2.0, that was attributed to tunnelling via deep levels in the forbidden gap. Impedance spectra shows the spectrum of the Impedance resistance that the curve does not represent a regular semicircle andthis indicates that the structure of the material is not regulated granules but rather is in a different form which is the nanowires. From Piezoelectric characterization, voltage increase with increase the force applied on Nanowires.


Introduction
: Hexagonal wurtzite structure of ZnO.

Abstract
Oxide nanowire arrays were studied for piezoelectric applications.Such as ZnO nanowire arrays growth on silicon substrate. The effects of thermal annealing on the optical properties of ZnO nanowires were prepared on sol-gel ZnO-seed-coated substrates. AFM images were found at 130°C well aligned vertically, and the well defined crystallographic planes, providing strong evidence that the nanowire arrays orientate along the c-axis. The annealing temperature of the ZnO thin film plays an important role on the microstructure of the ZnO grains and then the growth of the ZnO nanowire arrays. From PL spectra, an evident ultraviolet near-band edge emission peak at 382nm is observed.From (I-V) characteristic that the material behaves p-n junction diode, ideality factors >>2.0, that was attributed to tunnelling via deep levels in the forbidden gap. Impedance spectra shows the spectrum of the Impedance resistance that the curve does not represent a regular semicircle andthis indicates that the structure of the material is not regulated granules but rather is in a different form which is the nanowires. From Piezoelectric characterization, voltage increase with increase the force applied on Nanowires.
Keywords:C-axis ZnO nanowires; ZnO seed layer; Sol-Gel;AFM images; PL spectra; (I-V) characteristics; Ideal factor;Impedance spectra;Piezoelectric characterization In recent years, zinc oxide (ZnO) has attracted a lot of attention because of its interesting physical properties such as its wide and direct band gap (3.37eV), large exciton binding energy (60meV), high electron mobility, and high thermal conductivity [1], exhibiting near UV light emission, transparent conductivity, hexagonal crystal structure ( Figure 1). These features render ZnO suitable for several applications ranging from optoelectronics [2], piezoelectric and photovoltaic systems [3]. In this research we try to find a way to convert mechanical energy into electric power with the use of aligned zinc oxide (ZnO) nano wires. The mechanism of the power generator relies on the coupling of piezoelectric and semiconducting properties of ZnO as well as the formation of a Schottky barrier between the metal and ZnO contacts. One-dimensional ZnO nanostructures such as nano wires have been extensively studied for other applications including solar cells [4], ultraviolet (UV) light-emitting diodes [5], photonic crystals and transparent electrodes [6]. Several methods have been demonstrated to fabricate one-dimensional ZnO nanostructures, such as vapour liquid solid epitaxial (VLSE), chemical vapour deposition (CVD) [7]. However, the high temperatures required for these gas deposition techniques (above 500 0 C for CVD and 900 0 Cfor VLSE) and pulse laser deposition (PLD) [8], but these techniques still have some limitations for substrate size and the need for high temperature operation.
Recently, the growth of ZnO nano wires in phase solutions at low temperature (below 100 °C) was reported by using the hydrothermal process, the growth had been on glass, silicon wafer and plastic substrates [9]. This method shows that the shape of the ZnO nano wires was sensitive to the orientation of Si substrate via the use of ZnO nano particles as a seed layer. However, systematic research on the influence of quality characteristics of ZnO sol-gel thin films on the growth of ZnO nano wire arrays via hydrothermal method has rarely been reported. In this work, now catalytic method and ZnO, cost effective, non-catalytic method and ZnO sol-gel thin films were used as the seed layers with different temperatures annealing.

Upturned crystalline growth method is two phases:
A. Preparation seed layer thin films: The ZnO thin films served as the seed layers were deposited on silicon substrates by a sol-gel method [10]. A coating solution contained zinc acetate dehydrate (Zn (CH 3 COO)22H 2 O, Merck, 99.5% purity) and equivalent molar mono ethanolamine (MEA) (NH 2 CH 2 CH 2 OH, Merck, 99.5% purity) dissolved in 2-methoxyethanol (2MOE) (CH 3 OCH 2 CH 2 OH, Merck, 99.5% purity). The concentration of zinc acetate was chosen to be 0.5mol/L. The resulting solution was then stirred at 60 °C for 2h to yield a homogeneous solution, which served as the coating solution after being cooled to room temperature. Then the solution was coated onto p-type silicon (111) substrates by a spin coater at the rate of 1000rpm for 30s at room temperature. Subsequently, the films were preheated for 10min to remove the residual solvent. Then the layer film was annealed in a furnace at different temperatures ranging from 130 to 900 °C for 2h.

B.
Growth Vertical ZnO Nano wires arrays: After uniformly coating the silicon substrates with ZnO thin films, growth of ZnO nano wire arrays was achieved by suspending these ZnO seed-coated substrates upside down in a glass beaker filled with solution of 50mM zinc nitrate hexa hydrate (Zn(NO 3 ) 2· 6H 2 O, 98% purity) and 50mM hexamethylenetetramine (HMT) (C 6 H 12 N 4 , 99.5% purity). During the growth, the glass beaker was heated with a laboratory oven maintained at 60 °C for 12h. At the end of the growth period, the substrates were removed from the solution, then immediately rinsed with de-ionized water to remove any residual salt from the surface, and dried in air at room temperature.

Results and Discussion
Surface morphologies (AFM Images) Figure 2 shows the AFM images for the surface morphologies of ZnO nano wire arrays at different annealing temperatures of the thin films. It is notable that the ZnO nano wire arrays on the ZnO thin films annealed at 130 °C are well aligned vertically (Figure 2a), and the well defined crystallographic planes, providing a strong evidence that the nano wire arrays orientate along the c-axis. This implies its perfect c-axis orientation. As the annealing temperatures of the ZnO thin films increase from 130 to 900 °C, the diameters of the ZnO nano wire arrays increase from 10 to 80nm in average and its high ranging from 300 to 400nm. The reason may be that the high annealing temperature evidently increase the interaction among the grains and leads the grains to merge together to form bigger ZnO seeds, and thus increases the diameter of the ZnO nano wires      Figure 3-7 shows that at constant voltage, the current value of the voltage is increase than its value in case of voltage decrease there is a slow loop. This is due to the fact that while lifting the applied voltage, the ions on the trap level have moved to another more closely related crystalline structure leading to decreasing charge carriers during the decrease in applied voltage and thus the current decline. Note from the (I-V) characteristic that the material behaves p-n junction diode. As per the Sah-Noyce-Shockley theory [11], the forward current in a p-n junction is dominated by recombination of minority carriers injected into the neutral regions of the junction. This type of current gives an ideality factor of 1.0. Recombination of carriers in the space charge region, mediated by recombination centers located near the intrinsic Fermi level, results in an ideality factor of 2.0 [12]. The high ideality factors (n>>2.0) in LEDs or p-n junction diode were attributed to deeplevel-assisted tunneling, due to temperature-independent slopes of (log I)-versus-V plots. Ideality factors close to 2.0 were attributed to space charge region recombination, consistent with the Sah-Noyce-Shockley theory, due to temperature-dependent slopes of (log I)-versus-V plots. However, a comprehensive theory for the high ideality factors found experimentally in p-n junctions has not been presented. The ideal factor can be calculated by drawing the graph of Ln(I) with V as in Figure 8.   Where q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature, and n is the ideality factor. Where attention is given to the linear area of the curve [13]. The ideal factor values were arranged in Table 1 it is apparent that ideality factors >>2.0 can be measured, that was attributed to tunneling via deep levels in the forbidden gap. Impedance spectra measurements: Using a gain phase analyzer devise type (Schlumberger-SI1253) with detection resistance Rd. A variable frequency signal [0.1Hz-20KHz] was applied to the material and a fixed input voltage (V1=5v) was applied. To determine the spectrum of impedance spectra, the equation (2) can be used:  Figure 9 shows the curves are regular semicircles. So the structure of the granular material in the seed layer represents the equivalent circuit between the granules is intense and connected in parallel with the resistance. Figure 10 shows the spectrum of the Impedance resistance that the curve does not represent a regular semicircle and this indicates that the structure of the material is not regulated granules but rather is in a different form which is the nano wires [14]. The time of deceleration (τ) of the electron can be determined by drawing the real section of the impedance with frequency as shown in Figure 11. Since the deceleration time is equal to the inverted frequency at the top of the curve ( Table 2).